3D is coming to a datacenter near you, with all the action-packed excitement you can imagine.
No, not the 3D that enables crazed Texans to thrust whining chainsaws into your face at movie theaters. I mean three-dimensional chip-fabrication processes, which turn out to be one of the most promising avenues for jacking up the bit densities of NAND flash memory chips.
NAND flash is, of course, a datacenter workhorse these days, the basis for most of the solid state disk (SSD) products that enterprises are using to accelerate their databases, transaction processing systems, and big-data analytics. Appetite for SSD is nothing less than insatiable, it seems. Trouble is, NAND flash is starting to hit some limits in terms of how small its memory cells can be manufactured while still being able to retain individual bits of data. Smaller cells means denser chips, but further increases in density are starting to look more difficult.
So, chip makers are seeking ways of building up, along the vertical dimension, stacking memory cells on top of each other. Already, NAND flash is the chip process leader, employing the narrowest line widths -- around 19nm, with 15nm and 13nm on the drawing board. But only by building vertically can densities keep increasing as they have.
A variety of 3D NAND designs are being pursued. They go by names such as terabit cell array transistor (TCAT); vertical-stacked array transistor (VSAT); pipe-shaped bit cost scalable (P-BiCS); and vertical gate (VG) NAND. Each has its own pros and cons and all present serious design and manufacturing challenges.
Specifically, as flat, densely-packed 2D arrays of memory cells get stacked vertically, the potential increases that individual cells will electrically interfere with their neighbors -- to the left and right, the front and the back, and now, above and below, as well. That presents both chip designers and those making chip-fabrication equipment with some tough problems to solve.
Building such structures is not a matter of simply stacking chip dies (slabs of silicon) on top of each other. Instead, it's a matter of building, through an etching process, teeny-tiny cells one on top of the other -- in horizontal grids, of course, though also with tiny vertical shafts in place to accomodate the wires needed to brings electrical signals to each layer.
"Building 3D NAND structures is like trying to dig a one-kilometer-deep, three-kilometer-long trench with walls exactly three meters apart, through interleaved rock strata," engineering publication EDN explains, using a simile provided by Applied Materials, a maker of chip-fabrication equipment. In fact, EDN reports, Applied Materials is having to create new machines to etch these intricate NAND structures.
One company that has described its work in 3D NAND flash is Toshiba, which has opted for P-BiCS technology. As company engineers described it last year, Toshiba's plan is to build a structure that will initially comprise 16 layers of NAND cells. Chips with 128Gbit and 256Gbit capacities will be prototyped this year, but makers of storage systems won't get their hands on Toshiba's new chips before 2015, the company has stated. And that's if everything goes well.
Also working on 3D NAND flash is Macronix, which has described a design with 32 layers of cells that may eventually yield 1Tbit chips. Macronix is working with a proprietary cell design it calls BE-SONOS. Delivery schedule? It's not clear yet.
What is clear is that little of this will directly affect or matter to Corporate America's IT infrastructure managers as they shop for SSD. There's no need to really understand the microscopic details of chips to use them, is there? But as the appetite for fast, non-volatile semiconductor memory continues to grow, it may be comforting to know that the elves are working on cramming more bits into fewer cubic nanometers, and that the ultimate payoff from all that effort will be many more gigabits of flash capacity per dollar spent.
Who could ask for anything more?